13th Gen Raptor Lake CPUs Could Feature Significant Cache Size Increases

[{"selector":"#anim-81475c9f-0ab7-4dc7-886c-3c38e2d9d16a","keyframes":[{"transform":"scale(1)","offset":0},{"transform":"scale(1.05)","offset":0.33},{"transform":"scale(0.995)","offset":0.66},{"transform":"scale(1)","offset":1}],"delay":0,"duration":600,"easing":"ease-in-out","fill":"both","iterations":3}] 13th Gen Raptor Lake CPUs Could Feature Significant Cache Size Increases

[{"selector":"#anim-87c3b429-f4ef-4e2d-bfa3-db6c887344d7","keyframes":{"opacity":[0,1]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] [{"selector":"#anim-6e1e0daf-def5-4a14-9670-d6c045ac106c","keyframes":{"transform":["rotate(-360deg) translate3d(-120.06803%, 0px, 0) rotate(360deg)","rotate(-360deg) translate3d(0px, 0px, 0) rotate(360deg)"]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] 13th Gen CPUs could feature significant cache size increases.

[{"selector":"#anim-e29f0480-4fef-4152-ae51-d0a2b04683bc","keyframes":{"opacity":[0,1]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] [{"selector":"#anim-4f8f006c-537a-4293-8ec8-2f69a37ee072","keyframes":{"transform":["translate3d(-118.66666%, 0px, 0)","translate3d(0px, 0px, 0)"]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] Intel might add more L2 cache.

[{"selector":"#anim-ea167876-0176-4cb4-9612-57421b6c83fb","keyframes":{"opacity":[0,1]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] [{"selector":"#anim-d9249c3c-bbbb-4e2f-ad50-2ac3e6ae1972","keyframes":{"transform":["translate3d(-117.70492%, 0px, 0)","translate3d(0px, 0px, 0)"]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] It’s not easy to release faster CPUs each year for a company, Two relatively easier ways to go about it.

[{"selector":"#anim-b2219600-c5b2-44f9-84ba-a99bab4d6b5a","keyframes":{"opacity":[0,1]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] [{"selector":"#anim-9aff0ae4-704e-471d-988d-35b2102c0dfe","keyframes":{"transform":["translate3d(-117.76316%, 0px, 0)","translate3d(0px, 0px, 0)"]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] Either increase clock speeds or add more cache, Intel focuses on clock speeds while AMD works on increasing cache.

[{"selector":"#anim-36c70e39-591b-4500-8e4a-e2e2f7532827","keyframes":{"opacity":[0,1]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] [{"selector":"#anim-a55072aa-3f7d-41bd-8da5-ffb3c22f3858","keyframes":{"transform":["translate3d(-120.54795%, 0px, 0)","translate3d(0px, 0px, 0)"]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] They claimed 15% more performance gain by simply adding more L3 cache.

[{"selector":"#anim-6bd6dee9-29a2-447a-a6ea-0e58f528e24f","keyframes":{"opacity":[0,1]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] [{"selector":"#anim-38c24656-5404-4ff2-ad5d-63b08dcddb52","keyframes":{"transform":["translate3d(-120.54795%, 0px, 0)","translate3d(0px, 0px, 0)"]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] They are going to increase L2 cache rather than L3 in Raptor Lake CPUs.

[{"selector":"#anim-4b2bd024-72a2-4d00-a691-1543227b4faf","keyframes":{"opacity":[0,1]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] [{"selector":"#anim-b0f47a14-81df-40c4-8bc3-89b4c3f037dd","keyframes":{"transform":["translate3d(-120.89042%, 0px, 0)","translate3d(0px, 0px, 0)"]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] 68M cache is going to be the total amount of cached packed in the 13th Gen CPU, Leaked on twitter.

[{"selector":"#anim-2f5e62f8-8e07-4a91-b62b-20dbc56a2179","keyframes":{"opacity":[0,1]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] [{"selector":"#anim-81a126df-6dc2-44d8-9198-98a3e1d03dfc","keyframes":{"transform":["translate3d(-120.54795%, 0px, 0)","translate3d(0px, 0px, 0)"]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] A full Alder Lake die has a total of 44MB cache.

[{"selector":"#anim-1a099f36-f5e8-4dcc-9a4b-fbf073687762","keyframes":{"opacity":[0,1]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] [{"selector":"#anim-5f70a050-2347-4b8c-9a1b-440536629391","keyframes":{"transform":["translate3d(-120.54795%, 0px, 0)","translate3d(0px, 0px, 0)"]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] They might increase the total amount of available cache from 44MB to 68MB accounting to the rumors.

[{"selector":"#anim-f11ab275-eaf6-40a3-a38b-0db2a52237cc","keyframes":{"opacity":[0,1]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] [{"selector":"#anim-e18e3cb8-514d-44c9-b466-6b97d970fbc1","keyframes":{"transform":["translate3d(-120.54795%, 0px, 0)","translate3d(0px, 0px, 0)"]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] A Twitter user made up a picture of the cache structure of a hypothetical i9 13900k.

[{"selector":"#anim-7cc60968-ee8d-46d5-a263-3d495400caef","keyframes":{"opacity":[0,1]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] [{"selector":"#anim-62f9d8e4-eebe-4fa0-84c5-3a3d128decba","keyframes":{"transform":["translate3d(-120.89042%, 0px, 0)","translate3d(0px, 0px, 0)"]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] If that’s correct the L2 cache will increase to 2MB for each P core and 4MB for rach E core cluster.

[{"selector":"#anim-dbc13f47-9877-451d-bfbd-d2851a92f8d4","keyframes":{"opacity":[0,1]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] [{"selector":"#anim-661424de-95cd-4616-8cd4-91367c616bef","keyframes":{"transform":["translate3d(-120.54795%, 0px, 0)","translate3d(0px, 0px, 0)"]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] L2 will increase to 32MB for all cores and 36MB L3 cache for all cores.

[{"selector":"#anim-653b3699-5ab3-4800-b1fd-4f860bce6f5b","keyframes":{"opacity":[0,1]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] [{"selector":"#anim-4a41e580-2f0a-4d71-9b19-29f157d1b498","keyframes":{"transform":["translate3d(-120.54795%, 0px, 0)","translate3d(0px, 0px, 0)"]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] L2 cache offers a lot more bandwidth with lower latency compared to L3.

[{"selector":"#anim-e25b2a6a-40d3-4191-a291-8a19c415c058","keyframes":{"opacity":[0,1]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] [{"selector":"#anim-5225360e-8102-4e60-8801-4d41e396dbe2","keyframes":{"transform":["translate3d(-120.54795%, 0px, 0)","translate3d(0px, 0px, 0)"]},"delay":100,"duration":800,"easing":"cubic-bezier(0.2, 0.6, 0.0, 1)","fill":"both"}] Games can take advantage of that increase, if software is coded to take full advantage.